--- agp_i810.c	Thu Jun 16 15:11:15 2005
+++ agp_i810.c.new	Thu Jun 16 21:32:41 2005
@@ -70,7 +70,7 @@
 #define CHIP_I810 0	/* i810/i815 */
 #define CHIP_I830 1	/* 830M/845G */
 #define CHIP_I855 2	/* 852GM/855GM/865G */
-#define CHIP_I915 3	/* 915G */
+#define CHIP_I915 3	/* 915G/915GM */
 
 struct agp_i810_softc {
 	struct agp_softc agp;
@@ -139,6 +139,9 @@
 
 	case 0x25828086:
 		return ("Intel 82915G (915G GMCH) SVGA controller");
+
+	case 0x25928086:
+		return ("Intel 82915GM (915GM GMCH) SVGA controller");
 	};
 
 	return NULL;
@@ -171,6 +174,7 @@
 	case 0x35828086:
 	case 0x25728086:
 	case 0x25828086:
+	case 0x25928086:
 		devid -= 0x20000;
 		break;
 	};
@@ -233,7 +237,6 @@
 		case 0x35828086:
 		case 0x25628086:
 		case 0x25728086:
-		case 0x25828086:	/* XXX: Is this the right way? */
 			gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
 			if ((gcc1 & AGP_I830_GCC1_DEV2) == AGP_I830_GCC1_DEV2_DISABLED) {
 				if (bootverbose)
@@ -242,6 +245,17 @@
 			}
 			break;
 
+			/* i915G */
+		case 0x25828086:
+		case 0x25928086:
+			gcc1 = pci_read_config(bdev, AGP_I915_DEVEN, 4);
+			if ((gcc1 & AGP_I915_DEVEN_D2F0) == AGP_I915_DEVEN_D2F0_DISABLED) {
+				if (bootverbose)
+					printf("I915: disabled, not probing\n");
+				return ENXIO;
+			}
+			break;
+
 		default:
 			return ENXIO;
 		}
@@ -285,6 +299,7 @@
 		sc->chiptype = CHIP_I855;
 		break;
 	case 0x25828086:
+	case 0x25928086:
 		sc->chiptype = CHIP_I915;
 		break;
 	};
@@ -386,29 +401,31 @@
 	} else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915) {	/* CHIP_I855 */
 		/* The i855 automatically initializes the 128k gatt on boot. */
 		unsigned int gcc1, pgtblctl;
+		int steal;
+		steal = (sc->chiptype == CHIP_I855 ? 132 : 260);
 		
 		gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
 		switch (gcc1 & AGP_I855_GCC1_GMS) {
 			case AGP_I855_GCC1_GMS_STOLEN_1M:
-				sc->stolen = (1024 - 132) * 1024 / 4096;
+				sc->stolen = (1024 - steal) * 1024 / 4096;
 				break;
 			case AGP_I855_GCC1_GMS_STOLEN_4M: 
-				sc->stolen = (4096 - 132) * 1024 / 4096;
+				sc->stolen = (4096 - steal) * 1024 / 4096;
 				break;
 			case AGP_I855_GCC1_GMS_STOLEN_8M: 
-				sc->stolen = (8192 - 132) * 1024 / 4096;
+				sc->stolen = (8192 - steal) * 1024 / 4096;
 				break;
 			case AGP_I855_GCC1_GMS_STOLEN_16M: 
-				sc->stolen = (16384 - 132) * 1024 / 4096;
+				sc->stolen = (16384 - steal) * 1024 / 4096;
 				break;
 			case AGP_I855_GCC1_GMS_STOLEN_32M: 
-				sc->stolen = (32768 - 132) * 1024 / 4096;
+				sc->stolen = (32768 - steal) * 1024 / 4096;
 				break;
 			case AGP_I915_GCC1_GMS_STOLEN_48M: 
-				sc->stolen = (49152 - 132) * 1024 / 4096;
+				sc->stolen = (49152 - steal) * 1024 / 4096;
 				break;
 			case AGP_I915_GCC1_GMS_STOLEN_64M: 
-				sc->stolen = (65536 - 132) * 1024 / 4096;
+				sc->stolen = (65536 - steal) * 1024 / 4096;
 				break;
 			default:
 				sc->stolen = 0;
@@ -504,8 +521,8 @@
 	case CHIP_I855:
 		return 128 * 1024 * 1024;
 	case CHIP_I915:
-		temp = pci_read_config(sc->bdev, AGP_I915_GMADR, 4);
-		if (temp & (1 << 27)) {
+		temp = pci_read_config(dev, AGP_I915_MSAC, 1);
+		if ((temp & AGP_I915_MSAC_GMASIZE) == AGP_I915_MSAC_GMASIZE_128) {
 			return 128 * 1024 * 1024;
 		} else {
 			return 256 * 1024 * 1024;
@@ -563,21 +580,22 @@
 		}
 		break;
 	case CHIP_I915:
-		temp = pci_read_config(sc->bdev, AGP_I915_GMADR, 4);
+		temp = pci_read_config(dev, AGP_I915_MSAC, 1);
+		temp &= ~AGP_I915_MSAC_GMASIZE;
 
 		switch (aperture) {
 		case 128 * 1024 * 1024:
-			temp |= (1 << 27);
+			temp |= AGP_I915_MSAC_GMASIZE_128;
 			break;
 		case 256 * 1024 * 1024:
-			temp &= ~(1 << 27);
+			temp |= AGP_I915_MSAC_GMASIZE_256;
 			break;
 		default:
 			device_printf(dev, "bad aperture size %d\n", aperture);
 			return EINVAL;
 		}
 
-		pci_write_config(sc->bdev, AGP_I915_GMADR, temp, 4);
+		pci_write_config(dev, AGP_I915_MSAC, temp, 1);
 		break;
 	}
 
--- agpreg.h	Thu Jun 16 15:11:15 2005
+++ agpreg.h.new	Thu Jun 16 17:05:11 2005
@@ -240,6 +240,14 @@
 #define AGP_I915_GTTADR			0x1C
 #define AGP_I915_GCC1_GMS_STOLEN_48M	0x60
 #define AGP_I915_GCC1_GMS_STOLEN_64M	0x70
+#define AGP_I915_DEVEN			0x54
+#define AGP_I915_DEVEN_D2F0		0x08
+#define AGP_I915_DEVEN_D2F0_ENABLED	0x08
+#define AGP_I915_DEVEN_D2F0_DISABLED	0x00
+#define AGP_I915_MSAC			0x62
+#define AGP_I915_MSAC_GMASIZE		0x02
+#define AGP_I915_MSAC_GMASIZE_128	0x02
+#define AGP_I915_MSAC_GMASIZE_256	0x00
 
 /*
  * NVIDIA nForce/nForce2 registers
